有什么方法可以知道Linux中L1,L2,L3缓存和RAM的大小吗?


Answers:


23

如果已lshw安装:

$ sudo lshw -C memory

$ sudo lshw -C memory
...
  *-cache:0
       description: L1 cache
       physical id: a
       slot: Internal L1 Cache
       size: 32KiB
       capacity: 32KiB
       capabilities: asynchronous internal write-through data
  *-cache:1
       description: L2 cache
       physical id: b
       slot: Internal L2 Cache
       size: 256KiB
       capacity: 256KiB
       capabilities: burst internal write-through unified
  *-cache:2
       description: L3 cache
       physical id: c
       slot: Internal L3 Cache
       size: 3MiB
       capacity: 8MiB
       capabilities: burst internal write-back
  *-memory
       description: System Memory
       physical id: 2a
       slot: System board or motherboard
       size: 8GiB
     *-bank:0
          description: SODIMM DDR3 Synchronous 1334 MHz (0.7 ns)
          product: M471B5273CH0-CH9
          vendor: Samsung
          physical id: 0
          serial: 67010644
          slot: DIMM 1
          size: 4GiB
          width: 64 bits
          clock: 1334MHz (0.7ns)
     *-bank:1
          description: SODIMM DDR3 Synchronous 1334 MHz (0.7 ns)
          product: 16JTF51264HZ-1G4H1
          vendor: Micron Technology
          physical id: 1
          serial: 3749C127
          slot: DIMM 2
          size: 4GiB
          width: 64 bits
          clock: 1334MHz (0.7ns)

1
请包括答案的内容。不要只提及命令名称,而要显示其输出。
slm

lshw(当然,具有root权限运行)没有给我缓存信息。但lscpudmidecode工具给我的结果。
Shnd

19

lscpu

如果您只关心尺寸,请尝试lscpuutil-linux

$ lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                4
On-line CPU(s) list:   0-3
Thread(s) per core:    2
Core(s) per socket:    2
Socket(s):             1
NUMA node(s):          1
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 37
Model name:            Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz
Stepping:              5
CPU MHz:               1199.000
BogoMIPS:              5319.88
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              3072K
NUMA node0 CPU(s):     0-3

x86信息

还应该有一个名为x86info的软件包/命令。假设您拥有i386 / x86_64,x86info -c则应提供有关缓存的更多详细信息。

$ x86info -c
x86info v1.30.  Dave Jones 2001-2011
Feedback to <davej@redhat.com>.

Found 4 identical CPUs
Extended Family: 0 Extended Model: 2 Family: 6 Model: 37 Stepping: 5
Type: 0 (Original OEM)
CPU Model (x86info's best guess): Core i7 (Nehalem) [Clarkdale/Arrandale]
Processor name string (BIOS programmed): Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz

Cache info
 L1 Instruction cache: 32KB, 4-way associative. 64 byte line size.
 L1 Data cache: 32KB, 8-way associative. 64 byte line size.
 L2 (MLC): 256KB, 8-way associative. 64 byte line size.
TLB info
 Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries
 Instruction TLB: 4K pages, 4-way associative, 64 entries.
 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.
 Data TLB: 4KB pages, 4-way associative, 64 entries
 Data TLB: 4K pages, 4-way associative, 512 entries.
 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.
 Data TLB: 4KB pages, 4-way associative, 64 entries
 64 byte prefetching.
 Data TLB: 4K pages, 4-way associative, 512 entries.
Found unknown cache descriptors: dd 
Total processor threads: 4
This system has 1 dual-core processor with hyper-threading (2 threads per core) running at an estimated 2.65GHz

3

您可以尝试此命令。

$sudo dmidecode -t cache

$ sudo dmidecode -t cache | grep -iE "leve|installed"
    Configuration: Enabled, Socketed, Level 1
    Installed Size: 32 kB
    Installed SRAM Type: Asynchronous
    Configuration: Enabled, Socketed, Level 2
    Installed Size: 256 kB
    Installed SRAM Type: Burst
    Configuration: Enabled, Socketed, Level 3
    Installed Size: 3072 kB
    Installed SRAM Type: Burst

要查看RAM,只需添加其他开关即可-t memory

$ sudo dmidecode -t cache -t memory

参考文献


3

getconf

getconf -a | grep CACHE

给出:

LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  262144
LEVEL2_CACHE_ASSOC                 8
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  20971520
LEVEL3_CACHE_ASSOC                 20
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

或对于单个级别:

getconf LEVEL2_CACHE_SIZE

这个接口的优点是,它只是POSIX sysconfC函数的包装(缓存参数是非POSIX扩展名),因此也可以在C代码中使用它。

在Ubuntu 16.04中测试。

x86 CPUID指令

CPUID x86指令还提供了缓存信息,并且可以由用户级直接访问:https : //en.wikipedia.org/wiki/CPUID

glibc似乎在x86上使用了该方法。我还没有通过逐步调试/指令跟踪来确认,但是2.28的源代码sysdeps/x86/cacheinfo.c做到了:

__cpuid (2, eax, ebx, ecx, edx);

TODO现在创建一个最小的C示例,现在开始懒惰,请访问:https//stackoverflow.com/questions/14283171/how-to-receive-l1-l2-l3-cache-size-using-cpuid-instruction-in-x86

ARM还具有一种体系结构定义的机制,可通过诸如缓存大小ID寄存器(CCSIDR)之类的寄存器查找缓存大小,有关概述,请参见《ARMv8程序员手册》 11.6“缓存发现”。


2

sysfs自2008年以来,有一些特殊文件导出到/ sys Linux文件系统:

https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-devices-system-cpu

What:       /sys/devices/system/cpu/cpu*/cache/index*/<set_of_attributes_mentioned_below>
Date:       July 2014(documented, existed before August 2008)
Description:    Parameters for the CPU cache attributes

    allocation_policy:
        - WriteAllocate: allocate a memory location to a cache line
                 on a cache miss because of a write
        - ReadAllocate: allocate a memory location to a cache line
                on a cache miss because of a read
        - ReadWriteAllocate: both writeallocate and readallocate

    coherency_line_size: the minimum amount of data in bytes that gets
                 transferred from memory to cache

    level: the cache hierarchy in the multi-level cache configuration

    number_of_sets: total number of sets in the cache, a set is a
            collection of cache lines with the same cache index

    physical_line_partition: number of physical cache line per cache tag

    shared_cpu_list: the list of logical cpus sharing the cache

    shared_cpu_map: logical cpu mask containing the list of cpus sharing
            the cache

    size: the total cache size in kB

    type:
        - Instruction: cache that only holds instructions
        - Data: cache that only caches data
        - Unified: cache that holds both data and instructions

    ways_of_associativity: degree of freedom in placing a particular block
                of memory in the cache

    write_policy:
        - WriteThrough: data is written to both the cache line
                and to the block in the lower-level memory
        - WriteBack: data is written only to the cache line and
                 the modified cache line is written to main
                 memory only when it is replaced

身份证件:

What:       /sys/devices/system/cpu/cpu*/cache/index*/id
Date:       September 2016
Contact:    Linux kernel mailing list <linux-kernel@vger.kernel.org>
Description:    Cache id

    The id provides a unique number for a specific instance of
    a cache of a particular type. E.g. there may be a level
    3 unified cache on each socket in a server and we may
    assign them ids 0, 1, 2, ...

    Note that id value can be non-contiguous. E.g. level 1
    caches typically exist per core, but there may not be a
    power of two cores on a socket, so these caches may be
    numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...

我想知道为什么在我的机器上index0以及index1两者都level 1在内核v4.15上执行,这令人困惑。0索引预防性编码?:-)
Ciro Santilli新疆改造中心法轮功六四事件

1
@CiroSantilli华涌低端人口六四事件法轮功,(名称不发音),可能index0大约与带type数据的L1(L1数据缓存)有关,而index1大约与带type指令的L1(L1指令缓存)有关。然后index2是type Unifiedlevel2(二级缓存,可以存储数据和指令)
osgx

是的!我应该更耐心地阅读文档:-)
Ciro Santilli新疆改造中心法轮功六四事件

1

cpuid

另一个选项是cpuid程序。它使用CPUID说明,不需要root。它也可以在cpuidLinux内核模块中工作。

cache and TLB information (2):
   0x59: data TLB: 4K pages, 16 entries
   0xba: data TLB: 4K pages, 4-way, 64 entries
   0x4f: instruction TLB: 4K pages, 32 entries
   0xc0: data TLB: 4K & 4M pages, 4-way, 8 entries
   0x80: L2 cache: 512K, 8-way, 64 byte lines
   0x30: L1 cache: 32K, 8-way, 64 byte lines
   0x0e: L1 data cache: 24K, 6-way, 64 byte lines

请注意,在普通用户CPU上,L1和L2高速缓存是每个内核的,而L3高速缓存是由所有内核共享的。


0

如果您只想要L3,那么grep "cache size" < /proc/cpuinfo就足够了。

但是,由于在cpu拱之间共享L3缓存的方式不同,因此可能需要对其值进行归一化


也许您想删除对猫的无用使用。
maxschlepzig
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