我想创建一个特定的Verilog模块层次结构的示意图，以显示哪些块连接到哪些其他块。与Novas / Springsoft的Debussy / Verdi nschema工具非常相似，或者与许多提供RTL图形设计浏览器的EDA工具一样。
哪些工具区域可用于从verilog或vhdl定义或从其他一些基于文本的输入格式以编程方式绘制原理图？
如何从Verilog生成原理图框图图像文件？
Answers:
使用Yosys，这是一个免费且开源的HDL综合工具箱，具有额外的凉爽（和免费）功能（并且比当前的Vivado速度更快）（我是否在语音和啤酒中提到了Free？）（又很棒）！
获取yosys和xdot实用程序（通常是称为python-xdot的软件包的一部分）以及graphviz。
然后，在verilog文件中做类似的事情（让我们调用minifsm.v）：
module piggybank (
input clk,
input reset,
input [8:0] deposit,
input [8:0] withdrawal,
output [16:0] balance,
output success
);
reg [16:0] _balance;
assign balance = _balance;
wire [8:0] interest = _balance [16:9];
reg [5:0] time_o_clock;
localparam STATE_OPEN = 0;
localparam STATE_CLOSED = 1;
reg openness;
assign success = (deposit == 0 && withdrawal == 0) || (openness == STATE_OPEN && (withdrawal <= _balance));
always @(posedge clk)
if(reset) begin
_balance <= 0;
openness <= STATE_CLOSED;
time_o_clock <= 0;
end else begin
if (openness == STATE_CLOSED) begin
if(time_o_clock == 5'd7) begin
openness <= STATE_OPEN;
time_o_clock <= 0;
end else begin
time_o_clock <= time_o_clock + 1;
end
if (time_o_clock == 0) begin //add interest at closing
_balance <= _balance + interest;
end;
end else begin //We're open!
if(time_o_clock == 5'd9) begin // open for 9h
openness <= STATE_CLOSED;
time_o_clock <= 0;
end else begin
_balance <= (success) ? _balance + deposit - withdrawal : _balance;
time_o_clock <= time_o_clock + 1;
end
end // else: !if(openness == STATE_CLOSED)
end // else: !if(reset)
endmodule // piggybank
并运行yosys：
yosys
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.6+155 (git sha1 a72fb85, clang 3.7.0 -fPIC -Os)
加载verilog文件，然后检查层次结构，然后提取流程，进行优化，找到状态机，进行优化并显示图形：
yosys> read_verilog minifsm.v
… …
yosys> hierarchy -check;
yosys> proc;
yosys> opt;
yosys> fsm;
yosys> opt;
yosys> show;
你会得到像
使用show命令的不同选项，您还可以将图形保存到文件中。Yosys允许您在verilog，EDIF，BLIF，…中编写“扁平化”逻辑，为特定的技术平台（包括ArachnePnR支持的平台）进行合成和映射，并做更多有趣的事情。本质上，Yosys就像是让知道如何构建编译器的人编写Verilog合成器。