这是来自ATmega32数据表的报价: By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. 我打算使用8位ADC。问题是:我能走到200kHz以上多少?我在数据表中找不到有关此的任何信息。是否可以使用64或32的预分频器,从而在uC以16MHz运行时分别以250kHz或500kHz运行ADC而没有转换错误?超出规范的ADC可能带来什么后果?