用合成的ROM内核模拟一个简单的测试台

我对FPGA领域是一个全新的领域，并认为我将从一个非常简单的项目开始：一个4位7段解码器。我纯粹用VHDL编写的第一个版本（基本上是单个组合select，不需要时钟），并且似乎可以使用，但我也想尝试使用Xilinx ISE中的“ IP内核”功能。

因此，现在我正在使用“ ISE Project Explorer” GUI，并使用ROM内核创建了一个新项目。生成的VHDL代码为：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY SSROM IS
  PORT (
    clka : IN STD_LOGIC;
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
  );
END SSROM;

ARCHITECTURE SSROM_a OF SSROM IS
-- synthesis translate_off
COMPONENT wrapped_SSROM
  PORT (
    clka : IN STD_LOGIC;
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
  );
END COMPONENT;

-- Configuration specification
  FOR ALL : wrapped_SSROM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_2(behavioral)
    GENERIC MAP (
      c_addra_width => 4,
      c_addrb_width => 4,
      c_algorithm => 1,
      c_axi_id_width => 4,
      c_axi_slave_type => 0,
      c_axi_type => 1,
      c_byte_size => 9,
      c_common_clk => 0,
      c_default_data => "0",
      c_disable_warn_bhv_coll => 0,
      c_disable_warn_bhv_range => 0,
      c_enable_32bit_address => 0,
      c_family => "spartan3",
      c_has_axi_id => 0,
      c_has_ena => 0,
      c_has_enb => 0,
      c_has_injecterr => 0,
      c_has_mem_output_regs_a => 0,
      c_has_mem_output_regs_b => 0,
      c_has_mux_output_regs_a => 0,
      c_has_mux_output_regs_b => 0,
      c_has_regcea => 0,
      c_has_regceb => 0,
      c_has_rsta => 0,
      c_has_rstb => 0,
      c_has_softecc_input_regs_a => 0,
      c_has_softecc_output_regs_b => 0,
      c_init_file_name => "SSROM.mif",
      c_inita_val => "0",
      c_initb_val => "0",
      c_interface_type => 0,
      c_load_init_file => 1,
      c_mem_type => 3,
      c_mux_pipeline_stages => 0,
      c_prim_type => 1,
      c_read_depth_a => 16,
      c_read_depth_b => 16,
      c_read_width_a => 7,
      c_read_width_b => 7,
      c_rst_priority_a => "CE",
      c_rst_priority_b => "CE",
      c_rst_type => "SYNC",
      c_rstram_a => 0,
      c_rstram_b => 0,
      c_sim_collision_check => "ALL",
      c_use_byte_wea => 0,
      c_use_byte_web => 0,
      c_use_default_data => 0,
      c_use_ecc => 0,
      c_use_softecc => 0,
      c_wea_width => 1,
      c_web_width => 1,
      c_write_depth_a => 16,
      c_write_depth_b => 16,
      c_write_mode_a => "WRITE_FIRST",
      c_write_mode_b => "WRITE_FIRST",
      c_write_width_a => 7,
      c_write_width_b => 7,
      c_xdevicefamily => "spartan3e"
    );
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_SSROM
  PORT MAP (
    clka => clka,
    addra => addra,
    douta => douta
  );
-- synthesis translate_on

END SSROM_a;

它使用以下内容初始化：

memory_initialization_radix=2;
memory_initialization_vector=
0000001,
1001111,
0010010,
0000110,
1001100,
0100100,
0100000,
0001111,
0000000,
0000100,
0001000,
1100000,
0110001,
1000010,
0110000,
0111000,

它有三个引脚：clka，addra和douta。我还使用GUI生成了一个测试平台，然后对其进行了稍微的编辑，以使其在100 ns后更改输入：

   uut: SSROM PORT MAP (
          clka => clk,
          addra => addra,
          douta => douta
        );

   -- Clock process definitions
   clka_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      addra <= "0101";
      wait for 100 ns;

      wait;
   end process;

但是当我运行仿真时，douta信号的值始终是不确定的：

是什么赋予了？

您应该使用仿真工具查看SSROM模块内部的信号。有时查看实例化内部的输入可以帮助阐明问题所在的位置。也许您认为已连接的信号实际上没有。

要调查的另一件事是您的.mif文件。Xilinx在仿真中使用.mif文件来初始化用于仿真的存储器内容。如果您无意中移动或删除了.mif文件，则会看到类似的结果。